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NJU6624A/b NJU6624A/b n n 12-character 1-line dot matrix lcd controller driver 12-character 1-line dot matrix lcd controller driver n n maximum 60 icon display maximum 60 icon display n n serial direct interface with microprocessor serial direct interface with microprocessor n n display data ram display data ram - 14 x 8 bits - 14 x 8 bits : maximum 12-character 1-line display : maximum 12-character 1-line display n n character generator rom character generator rom - 7,840 bits - 7,840 bits : 224 characters for 5 x 7 dots : 224 characters for 5 x 7 dots n n character generator ram character generator ram - 1,120 bits - 1,120 bits : 32 patterns( 5 x 7 dots ) : 32 patterns( 5 x 7 dots ) n n icon display ram icon display ram - maximum 60 icons - maximum 60 icons n n high voltage lcd driver high voltage lcd driver : 8-common / 71-segment : 8-common / 71-segment n n duty and bias ratio duty and bias ratio : 1/8 duty, 1/4 bias : 1/8 duty, 1/4 bias n n master/slave function master/slave function :NJU6624A : master, nju6624b : slave :NJU6624A : master, nju6624b : slave n n useful instruction set useful instruction set : clear display, address home, display on/off cont., display blink, : clear display, address home, display on/off cont., display blink, address shift, character shift, dot shift, keyscan on/off cont. e.t.c. address shift, character shift, dot shift, keyscan on/off cont. e.t.c. n n 32key input (4x8 keyscan) 32key input (4x8 keyscan) n n g g eneral output port (4 ports) eneral output port (4 ports) n n power on initialization / hardware reset power on initialization / hardware reset n n bleeder resistance on-chip bleeder resistance on-chip n n software contrast control(16 step) software contrast control(16 step) n n oscillation circuit on-chip oscillation circuit on-chip n n low power consumption low power consumption n n operating voltage --- 2.4 to 5.5 v operating voltage --- 2.4 to 5.5 v n n package outline --- qfp 100 package outline --- qfp 100 n n c-mos technology c-mos technology g g package outline package outline g g general description general description mar.2000 mar.2000 ver.1 ver.1 g g features features the NJU6624A/b is a dot matrix lcd controller driver for 12-character the NJU6624A/b is a dot matrix lcd controller driver for 12-character 1-line with icon display in single chip. 1-line with icon display in single chip. it contains bleeder resistance, general output port, keyscan circuit, it contains bleeder resistance, general output port, keyscan circuit, cr oscillator, microprocessor interface circuit, instruction decoder con- cr oscillator, microprocessor interface circuit, instruction decoder con- troller, character generator rom/ram, high voltage operation com- troller, character generator rom/ram, high voltage operation com- mon and segment drivers, and others. mon and segment drivers, and others. the character generator rom consisting of 7,840 bits stores 224 kinds the character generator rom consisting of 7,840 bits stores 224 kinds of character font. each 1,120 bits cg ram and icon display ram of character font. each 1,120 bits cg ram and icon display ram can store 32 kinds of special character displayed on the dot matrix can store 32 kinds of special character displayed on the dot matrix display area or 60 kinds of icon on the icon display area. display area or 60 kinds of icon on the icon display area. the 8-common (7 for character, 1 for icon) and 71-segment drivers the 8-common (7 for character, 1 for icon) and 71-segment drivers operate 12-character 1-line with 60 icon lcd display and led driver operate 12-character 1-line with 60 icon lcd display and led driver drives 4 led which can use like as indicator. drives 4 led which can use like as indicator. the 16th display contrast control function is incorporated. therefore, the 16th display contrast control function is incorporated. therefore, the contrast adjustment is operated easily by only simple power sup- the contrast adjustment is operated easily by only simple power sup- ply circuit on-chip. ply circuit on-chip. the complete cr oscillator requires no external components. the complete cr oscillator requires no external components. the serial interface which operates by 1mhz, communicates with ex- the serial interface which operates by 1mhz, communicates with ex- ternal mcu. ternal mcu. as an outstanding feature, NJU6624A/b realizes the horizontal smooth as an outstanding feature, NJU6624A/b realizes the horizontal smooth scroll of characters by combination of instructions. scroll of characters by combination of instructions. the combination of NJU6624A as the master and nju6624b as the the combination of NJU6624A as the master and nju6624b as the slave drive the 12-character and 2-line lcd panel or 24-character 1- slave drive the 12-character and 2-line lcd panel or 24-character 1- line in 1/8 duty. line in 1/8 duty. 12-character 1-line dot matrix lcd 12-character 1-line dot matrix lcd controller driver with smooth scroll function controller driver with smooth scroll function NJU6624A/bfg1 NJU6624A/bfg1 preliminary preliminary
NJU6624A/b NJU6624A/b g g block diagram block diagram g g pin configuration pin configuration c r o s c c i r c u i t i n s t r u c t i o n d e c o d e r ( i d ) l a t c h s h i f t r e g . d r i v e r c o m m o n d r i v e r s e g m e n t 8 b i t 7 1 b i t 1 4 x 8 b i t s c h a r a c t e r g e n e r a t o r r a m ( c g r a m ) c h a r a c t e r g e n e r a t o r r o m ( c g r o m ) i c o n d i s p l a y r a m ( m k r a m ) t i m i n g g e n . 1 2 x 5 b i t s 5 x 7 x 3 2 b i t s 7 , 8 4 0 b i t s s e r i a l t o p a r a l l e l c o n v e r t o r i / o b u f f e r p o w e r o n r e s e t r e s e t d i s p l a y d a t a r a m ( d d r a m ) o u t p u t b u f f e r l e d p o r t r e g i s t e r i n s t r u c t i o n r e g i s t e r ( i r ) a d d r e s s c o u n t e r d a t a r e g i s t e r ( i r ) r e q s c l c o m 1 s e g 1 t o c o m 7 t o s e g 7 1 c s d a t a / c o m m k r e s e t v s s v l c d v 1 v 2 ( v 3 ) v 4 r b r b p 0 t o p 3 0 s c 1 v s s v l c d 2 v l c d 1 k e y s c a n c i r c u i t k 0 t o k 3 r b r b v l c d 1 n j u 6 6 2 4 a / b f g 1 1 v 1 s e g 7 0 s e g 6 9 s e g 6 7 s e g 6 8 s e g 6 6 s e g 6 5 s e g 6 3 s e g 6 4 s e g 6 2 s e g 6 1 s e g 6 0 s e g 5 9 s e g 5 2 s e g 5 1 s e g 5 0 s e g 4 9 s e g 4 8 s e g 4 7 s e g 4 6 s e g 4 5 s e g 4 4 s e g 4 2 s e g 4 3 s e g 4 1 s e g 4 0 s e g 3 8 s e g 3 9 s e g 3 7 s e g 3 6 s e g 3 5 s e g 3 4 s e g 9 s e g 1 0 s e g 1 1 s e g 1 3 s e g 1 2 s e g 1 4 s e g 1 5 s e g 1 7 s e g 1 6 s e g 1 8 s e g 2 6 s e g 1 9 s e g 2 7 s e g 2 0 s e g 2 2 s e g 2 1 s e g 2 3 s e g 2 4 s e g 2 5 v d d o s c 1 c s s c l d a t a r e s e t p 1 p 0 p 2 p 3 c o m 1 v s s c o m 2 s e g 1 / s 0 c o m 3 c o m 4 c o m 6 c o m 5 c o m 7 c o m m k r e q k 1 k 0 k 2 k 3 s e g 2 / s 1 s e g 3 / s 2 s e g 4 / s 3 s e g 5 / s 4 s e g 6 / s 5 s e g 7 / s 6 s e g 8 / s 7 s e g 3 2 s e g 3 3 s e g 2 8 s e g 2 9 s e g 3 0 s e g 3 1 s e g 5 8 s e g 5 7 s e g 5 6 s e g 5 5 s e g 5 4 s e g 5 3 s e g 7 1 v l c d 2 v 2 v 4
NJU6624A/b NJU6624A/b no. symbol i/o f u n c t i o n 2,13 vdd,vss - power source:vdd=+5v,gnd:vss=0v 1 vlcd1 i lcd driving voltage input terminal 100 99 98 97 vlcd2 v1 v2 v4 i lcd driving voltage stabilization capacitor terminals. connect the capacitor between vlcd2 and vss, v1 and vss, v2 and vss, v4 and vss. typ. : 0.1uf 3 osc1 i system clock input terminal this terminal should be open for internal clock operation. 11 cs i chip select signal input of serial i/f. 10 scl i sift clock input of serial i/f. 9 data i serial data input of serial i/f. 12 reset i reset terminal. when the "l" level is input over than 1.2ms to this terminal, the system will be reset ( at f osc 145khz ). 4-7 p0-p3 o general output port led driver drives led as indicator on athers. 8 req o key request signal output terminal. 14-17 k0-k3 i key scanning input terminals. 18-25 seg 1 /s 0 - seg 8 /s 7 o lcd segment driving signal output / key scanning output terminals. 26-88 seg 9- seg 71 o lcd segment driving signal output terminals 89-95 com 1- com 7 o lcd common driving signal output terminals 96 commk o icon common driving signal output terminals g g terminal description terminal description
NJU6624A/b NJU6624A/b g g functional description functional description (1-1)register (1-1)register the NJU6624A/b incorporates two 8-bit registers, an instruction register(ir) and a data register(dr). the the NJU6624A/b incorporates two 8-bit registers, an instruction register(ir) and a data register(dr). the register (ir) stores instruction codes such as "clear display" and "cursor shift" or address data for display data register (ir) stores instruction codes such as "clear display" and "cursor shift" or address data for display data ram(dd ram), character generator ram(cg ram) and icon display ram (mk ram). ram(dd ram), character generator ram(cg ram) and icon display ram (mk ram). the register(dr) is a temporary register, the data in the register(dr) is written into the dd ram, cg ram or the register(dr) is a temporary register, the data in the register(dr) is written into the dd ram, cg ram or mk ram. mk ram. the data in the register(dr) written by the mpu is transferred automatically to the dd ram, cg ram or mk the data in the register(dr) written by the mpu is transferred automatically to the dd ram, cg ram or mk ram by internal operation. ram by internal operation. these two registers are selected by the selection signal rs as shown below. these two registers are selected by the selection signal rs as shown below. (1-2)address counter (ac) (1-2)address counter (ac) the address counter(ac) addresses the dd ram, cg ram or mk ram. the address counter(ac) addresses the dd ram, cg ram or mk ram. when the address setting instruction is written into the register(ir), the address information is transferred from when the address setting instruction is written into the register(ir), the address information is transferred from register(ir) to the counter(ac). the selection of either the dd ram, cg ram or mk ram is also determined by register(ir) to the counter(ac). the selection of either the dd ram, cg ram or mk ram is also determined by this instruction. this instruction. after writing (or reading) the display data to (or from) the dd ram, cg ram or mk ram, the counter(ac) incre- after writing (or reading) the display data to (or from) the dd ram, cg ram or mk ram, the counter(ac) incre- ments (or decrements) automatically. ments (or decrements) automatically. (1-3)display data ram (dd ram) (1-3)display data ram (dd ram) the display data ram (dd ram) consist of 14x 8 bits stores up to 14-character display data represented in 8-bit the display data ram (dd ram) consist of 14x 8 bits stores up to 14-character display data represented in 8-bit code. (2 out of the 14characters are used for scroll ram.) code. (2 out of the 14characters are used for scroll ram.) the dd ram address data set in the address counter(ac) is represented in hexadecimal. the dd ram address data set in the address counter(ac) is represented in hexadecimal. (example) dd ram address " 08 " (example) dd ram address " 08 " higher lower ac ac 4 ac 3 ac 2 ac 1 ac 0 hex. hex. 0 1 0 0 0 8 8 0 0 when the display shift is performed,the dd ram address changes as follows: when the display shift is performed,the dd ram address changes as follows: ( left shift display ) ( left shift display ) 0d 00 01 02 03 04 05 06 07 08 09 0a 0b 0c =>(0e) ( right shift display ) ( right shift display ) the character generator rom (cg rom) generates 5 x 7 dots character pattern represented in 8-bit character the character generator rom (cg rom) generates 5 x 7 dots character pattern represented in 8-bit character code. code. the storage capacity is up to 224 kinds of 5 x 7 dots character pattern(available address is (20) the storage capacity is up to 224 kinds of 5 x 7 dots character pattern(available address is (20) h h through (ff) through (ff) h h ). ). the correspondence between character code and standard character pattern of NJU6624A/b is shown in table 2. the correspondence between character code and standard character pattern of NJU6624A/b is shown in table 2. user-defined character patterns (custom font) are also available by mask option. user-defined character patterns (custom font) are also available by mask option. ( ( 1-4)character generator rom (cg rom) 1-4)character generator rom (cg rom) the relation between dd ram address and display position on the lcd is shown below. the relation between dd ram address and display position on the lcd is shown below. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -display position 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d -dd ram address (hex.) (00)<= 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 00 | | scroll ram | | scroll ram
NJU6624A/b NJU6624A/b table 2. cg rom character pattern ( rom version -02 ) table 2. cg rom character pattern ( rom version -02 )
NJU6624A/b NJU6624A/b (1-5)character generator ram ( cg ram ) (1-5)character generator ram ( cg ram ) the character generator ram ( cg ram ) can store any kind of character pattern in 5 x 7 dots written by the user the character generator ram ( cg ram ) can store any kind of character pattern in 5 x 7 dots written by the user program to display user's original character pattern. the cg ram can store 32 kind of character in 5 x 7 dots program to display user's original character pattern. the cg ram can store 32 kind of character in 5 x 7 dots mode. mode. to display user's original character pattern stored in the cg ram, the address data (00) to display user's original character pattern stored in the cg ram, the address data (00) h h -(1f) -(1f) h h should be written should be written to the dd ram as shown in table 2. to the dd ram as shown in table 2. table 3. shows the correspondence among the character pattern, cg ram address and data. table 3. shows the correspondence among the character pattern, cg ram address and data. table 3. correspondence of cg ram address, dd ram character code table 3. correspondence of cg ram address, dd ram character code and cg ram character pattern( 5 x 7 dots ) and cg ram character pattern( 5 x 7 dots ) notes : notes : 1. character code bit 0 to 4 correspond to the cg ram address bit 3 to 7(5bits:32 patterns). 1. character code bit 0 to 4 correspond to the cg ram address bit 3 to 7(5bits:32 patterns). 2. cg ram address 0 to 2 designate character pattern line position. the 8th line is don't care line. 2. cg ram address 0 to 2 designate character pattern line position. the 8th line is don't care line. in case of input cg ram data continuously, invalid address are cursor position automatically. in case of input cg ram data continuously, invalid address are cursor position automatically. 3. character pattern row position correspond to the cg ram data bits 0 to 4 are shown above. 3. character pattern row position correspond to the cg ram data bits 0 to 4 are shown above. 4. cg ram character patterns are selected when character code of dd ram bits 5 to 7 are all "0" 4. cg ram character patterns are selected when character code of dd ram bits 5 to 7 are all "0" and these are addressed by character code bits 0 and 1. and these are addressed by character code bits 0 and 1. 5. "1" for cg ram data corresponds to display on and "0" to display off. 5. "1" for cg ram data corresponds to display on and "0" to display off. *=don't care *=don't care character code (dd ram data) cg ram address character pattern (cg ram data) 7 6 5 4 3 2 1 0 upperbit lower bit 7 6 5 4 3 2 1 0 upperbit lower bit 4 3 2 1 0 upper lower bit bi t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 character pattern example(1) <= cursor position 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 character pattern example(2) <= cursor position 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 * * * * * 1 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 * * * * *
NJU6624A/b NJU6624A/b com1 com1 com2 com2 com3 com3 com4 com4 com5 com5 com6 com6 com7 com7 commk commk seg seg 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 10 11 12 - - - - - - - - 6 6 76 76 8697071 8697071 (1-6)icon display ram (mk ram) (1-6)icon display ram (mk ram) the NJU6624A/b can display maximum 60 icons. the NJU6624A/b can display maximum 60 icons. the icon display can be controlled by writing the data in mk ram corresponds to the icon. the icon display can be controlled by writing the data in mk ram corresponds to the icon. the relation between mk ram address and icon display position is shown below: the relation between mk ram address and icon display position is shown below: table 4. correspondence among icon position, mk ram address and data table 4. correspondence among icon position, mk ram address and data mk ram address (10 h -1b h ) bits for icon display position d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0000 10 h 0 0 0 "1" "2" "3" "4" "5" 1 0001 11 h 0 0 0 "5" "7" "8" "9" "10" 1 0010 12 h 0 0 0 "11" "12" "13" "14" "15" 1 0011 13 h 0 0 0 "16" "17" "18" "19" "20" : : : 1 1011 1b h 0 0 0 "56" "57" "58" "59" "60" notes notes :there is no icon, on the segment terminals which are six times number of tines. (6th, 12th, 18th, 24th.... ) :there is no icon, on the segment terminals which are six times number of tines. (6th, 12th, 18th, 24th.... ) - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? 60 60 1 1
NJU6624A/b NJU6624A/b (1-7)timing generator (1-7)timing generator the timing generator generates a timing signals for the dd ram, cg ram and mk ram and other internal the timing generator generates a timing signals for the dd ram, cg ram and mk ram and other internal circuits. circuits. ram read timing for the display and internal operation timing for mpu access are separately generated, so that ram read timing for the display and internal operation timing for mpu access are separately generated, so that they may not interfere with each other. they may not interfere with each other. therefore, when the data write to the dd ram for example, there will be no undesirable influence, such as flicker- therefore, when the data write to the dd ram for example, there will be no undesirable influence, such as flicker- ing, in areas other than the display area. ing, in areas other than the display area. (1-8)lcd driver (1-8)lcd driver lcd driver consists of 8-common driver and 71-segment driver. lcd driver consists of 8-common driver and 71-segment driver. the character pattern data are latched to the addressed segment-register respectively. this latched data controls the character pattern data are latched to the addressed segment-register respectively. this latched data controls display driver to output lcd driving waveform. display driver to output lcd driving waveform. note) display note) display the NJU6624A/b generate ?space? automatically on the segment terminals. which are six times number of the NJU6624A/b generate ?space? automatically on the segment terminals. which are six times number of lines, regardless the smooth scroll function. in busy of the smooth scroll operation, this ?space? scrolls also with lines, regardless the smooth scroll function. in busy of the smooth scroll operation, this ?space? scrolls also with characters, there is no icon on the segment terminals which are six times number of lines. characters, there is no icon on the segment terminals which are six times number of lines. the loot number of the loot number of segment is 71, so that segment is 71, so that ?space? is not here. ?space? is not here. ?space? is generated when data ?space? is generated when data read out from cgrom or cgram read out from cgrom or cgram com1 com1 com2 com2 com3 com3 com4 com4 com5 com5 com6 com6 com7 com7 commk commk seg seg 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 10 11 12 - - - - - - - - 6 6 76 76 8697071 8697071 - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ? - - - - ?
NJU6624A/b NJU6624A/b s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 seg4/s3 seg4/s3 seg5/s4 seg5/s4 seg6/s5 seg6/s5 seg3/s2 seg3/s2 seg2/s1 seg2/s1 seg1/s0 seg1/s0 seg7/s6 seg7/s6 seg8/s7 seg8/s7 req req -example keyscan -example keyscan tks tks (1-9)keyscan circuit (1-9)keyscan circuit the keyscan circuit consists of a detector block of key pressing and a fetching block of key status. it scans 4x8 the keyscan circuit consists of a detector block of key pressing and a fetching block of key status. it scans 4x8 key matrix and fetches conditions of 32 keys. furthermore, it operates correctly against the key roll over input. key matrix and fetches conditions of 32 keys. furthermore, it operates correctly against the key roll over input. -request signal output -request signal output when the NJU6624A/b detect the key-in by the key scan circuit, it outputs ?h? signal as the request signal from when the NJU6624A/b detect the key-in by the key scan circuit, it outputs ?h? signal as the request signal from the ?req? terminal to notice the key pressing information to an application system. the ?req? terminal to notice the key pressing information to an application system. the request signal resets to ?l? level before 2 clock of next scanning. the request signal resets to ?l? level before 2 clock of next scanning. -key data input terminal and segment terminal -key data input terminal and segment terminal keyscan signal output terminals operate as segment terminals (seg1 to seg8) also and keyscan signals are keyscan signal output terminals operate as segment terminals (seg1 to seg8) also and keyscan signals are output in interval period of segment signals. key data input terminals (k0 to k3) are pulled up to vdd in busy of output in interval period of segment signals. key data input terminals (k0 to k3) are pulled up to vdd in busy of keyscan operation (tks). in this period, terminals of seg9 to seg71 output the voltage of v2 or v keyscan operation (tks). in this period, terminals of seg9 to seg71 output the voltage of v2 or v lcd2 lcd2 . . -keyscan off mode -keyscan off mode keyscan operation is turned on or off by the instruction. in case of keyscan off, the detector of key pressing keyscan operation is turned on or off by the instruction. in case of keyscan off, the detector of key pressing is not operating and key data input terminals (k0 to k3) are not pulled up during the period of keyscan (tks). in is not operating and key data input terminals (k0 to k3) are not pulled up during the period of keyscan (tks). in the period of keyscan (tks), all of segment terminals (seg1 to seg71) output the voltage of v2 or v the period of keyscan (tks), all of segment terminals (seg1 to seg71) output the voltage of v2 or v lcd2 lcd2 . . -contents of key register renewal -contents of key register renewal contents of key register are ?0000 0000? in case of no key operation. contents of key register are not changed in contents of key register are ?0000 0000? in case of no key operation. contents of key register are not changed in busy of key data reading operation. key data is fetched into the key register after 2 clock of the end of a keyscan busy of key data reading operation. key data is fetched into the key register after 2 clock of the end of a keyscan cycle and kept by the start of next cycle. cycle and kept by the start of next cycle.
NJU6624A/b NJU6624A/b scaned 8-bit data of key are read out through the srial i/f. scaned 8-bit data of key are read out through the srial i/f. -key status fetching timing -key status fetching timing key status is fetched at third quarter of ?l? period (tkp) of scan signals (s0 to s7) as shown below; key status is fetched at third quarter of ?l? period (tkp) of scan signals (s0 to s7) as shown below; s0 s0 s1 s1 tkp tkp 3/4tkp 3/4tkp fetching timing fetching timing tkp tkp 3/4tkp 3/4tkp -keyscan data format -keyscan data format keyscan output data kh2 kh1 kh0 s7 1 1 1 s6 1 1 0 s5 1 0 1 s4 1 0 0 s3 0 1 1 s2 0 1 0 s1 0 0 1 s0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ms1 ms0 1 0 0 1 1 1 kl3 kl2 kl1 kl0 0 kh2 kh1 kh0 | k3 to k0 | | s7 to s0 | example 1. one key is pressed example 1. one key is pressed read out data read out data o n o f f n j u 6 6 2 4 s 3 s 0 s 1 s 2 s 7 s 4 s 5 s 6 k 0 k 3 k 1 k 2 when a key on the key matrix is pressed, the bit corresponding to terminals (k3 to k0, s7 to s0) connected the when a key on the key matrix is pressed, the bit corresponding to terminals (k3 to k0, s7 to s0) connected the switch goes to ?1? and another bits go to ?0?. switch goes to ?1? and another bits go to ?0?. in case of example 1, when the switch connecting to k2 and s2 is pressed, bit(d6) corresponding to k2 and in case of example 1, when the switch connecting to k2 and s2 is pressed, bit(d6) corresponding to k2 and bit(d1) corresponding to s2 go to ?1? but another bits go to ?0?. bit(d1) corresponding to s2 go to ?1? but another bits go to ?0?. vss vss vlcd2 vlcd2 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ms1 ms0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 | k3 to k0 | | s7 to s0 |
NJU6624A/b NJU6624A/b the key roll over input is the vertical line as shown below (example 2) can be accepted with the keyscan circuit. the key roll over input is the vertical line as shown below (example 2) can be accepted with the keyscan circuit. but in case of example 3, the key roll over input in the horizontal line can not be accepted. but in case of example 3, the key roll over input in the horizontal line can not be accepted. the key roll over input must be taken care for key data judgement. the key roll over input must be taken care for key data judgement. o n o f f n j u 6 6 2 4 s 3 s 0 s 1 s 2 s 7 s 4 s 5 s 6 k 0 k 3 k 1 k 2 o n o f f n j u 6 6 2 4 s 3 s 0 s 1 s 2 s 7 s 4 s 5 s 6 k 0 k 3 k 1 k 2 note : in case of can not read out correct. note : in case of can not read out correct. example 2. the key roll over input (1) example 2. the key roll over input (1) read out data read out data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ms1 ms0 1 0 0 1 1 1 1 1 0 0 0 0 1 0 | k3 to k0 | | s7 to s0 | example 3. the key roll over input (2) example 3. the key roll over input (2)
NJU6624A/b NJU6624A/b (2)power on initialization by internal circuits (2)power on initialization by internal circuits (2-1)initialization by internal reset circuits (2-1)initialization by internal reset circuits the NJU6624A/b is automatically initialized by internal power on initialization circuits when the NJU6624A/b is automatically initialized by internal power on initialization circuits when the power is turned on. in the internal power on initialization, following instructions are executed. during the the power is turned on. in the internal power on initialization, following instructions are executed. during the internal power on initialization, the busy flag (bf) is "1" and this status is kept 1.5ms (fosc=145khz) after v internal power on initialization, the busy flag (bf) is "1" and this status is kept 1.5ms (fosc=145khz) after v dd dd rises to 2.4v. rises to 2.4v. initialization flow is shown below: initialization flow is shown below: note : if the condition of power supply rise time described in the electrical characteristics is not satisfied, the note : if the condition of power supply rise time described in the electrical characteristics is not satisfied, the internal power on initialization circuits will not operated and initialization will not performed. internal power on initialization circuits will not operated and initialization will not performed. in this case the initialization by mpu software is required. in this case the initialization by mpu software is required. (2-2)initialization by hardware (2-2)initialization by hardware -timing chart -timing chart external over 1.2ms reset signal 250us busy d=0 d=0 :display off :display off m=0 m=0 :icon off :icon off b=0 b=0 :cursor blink off :cursor blink off i/d=1 :increment by 1 i/d=1 :increment by 1 s=0 :no shift s=0 :no shift the NJU6624A/b incorporates reset terminal to initialize the all system. when the "l" level input over 1.2ms to the NJU6624A/b incorporates reset terminal to initialize the all system. when the "l" level input over 1.2ms to the reset terminal, reset sequence is executed. in this time, busy signal output during 250us (fosc=145khz) the reset terminal, reset sequence is executed. in this time, busy signal output during 250us (fosc=145khz) after reset terminal goes to "h". during this 250us period, any other instruction must not be input to the after reset terminal goes to "h". during this 250us period, any other instruction must not be input to the NJU6624A/b. NJU6624A/b. display on/off control entry mode set set static port contrast control set display mode clear display end ac=00h ac=00h p3-p0=0000 p3-p0=0000 :all static port output signal is ?l?. :all static port output signal is ?l?. e.v.r. value=0000 e.v.r. value=0000 : vlcd low : vlcd low k=1 k=1 keyscan on keyscan on df=0 df=0 release the power down mode release the power down mode
NJU6624A/b NJU6624A/b (3)combination of NJU6624A(master) and nju6624b(slave) (3)combination of NJU6624A(master) and nju6624b(slave) the combination of NJU6624A and b realizes 24character-1line display in 1/8 duty driving. the combination of NJU6624A and b realizes 24character-1line display in 1/8 duty driving. the instruction sets of version a and b are not so same (refer the instruction table) that the application does not the instruction sets of version a and b are not so same (refer the instruction table) that the application does not need to separate the signal lines to mcu. need to separate the signal lines to mcu. therefore, minimum lines (only 5-wires) realize the separately control for version a and b in the combined applica- therefore, minimum lines (only 5-wires) realize the separately control for version a and b in the combined applica- tion. tion. (3-1)a point to notice of master / slave connection (3-1)a point to notice of master / slave connection the NJU6624A of master lsi and the b of slave lsi don?t synchronize the frame frequency, so that the timings of the NJU6624A of master lsi and the b of slave lsi don?t synchronize the frame frequency, so that the timings of blinking between version a and b are not synchronized. blinking between version a and b are not synchronized. (3-2)panel composition of master / slave mode at smooth scroll. (3-2)panel composition of master / slave mode at smooth scroll. though the NJU6624A/b generate the space for smooth scroll operation automatically, it does not generate a though the NJU6624A/b generate the space for smooth scroll operation automatically, it does not generate a space at the right side position by 12th character. therefore, when the scroll is operated on the 1-line lcd panel space at the right side position by 12th character. therefore, when the scroll is operated on the 1-line lcd panel with normal wiring by one driver control, a space after the last character is lacked. with normal wiring by one driver control, a space after the last character is lacked. in case of combination application using NJU6624A and b, when the smooth scroll operate on the 1-line lcd, the in case of combination application using NJU6624A and b, when the smooth scroll operate on the 1-line lcd, the data should be set to overlap the memory area which are (0c)h and (0d)h of a and (01)h and (02)h of b, and data should be set to overlap the memory area which are (0c)h and (0d)h of a and (01)h and (02)h of b, and seg1 to seg5 of nju6624b should not be wired on the lcd panel for the blank display between the character. seg1 to seg5 of nju6624b should not be wired on the lcd panel for the blank display between the character. therefore, the maximum display size is 23-character 1-line in case of this application. therefore, the maximum display size is 23-character 1-line in case of this application. 07 08 09 0a 0b 0c 0d "n" "j" "u" "6" "6" "2" 00 01 02 03 04 05 "6" "6" "2" "4" not use not use NJU6624A internal ddram NJU6624A internal ddram scroll ram scroll ram seg seg 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 10 11 12 13 14 15 16 17 18 nc nc nc nc nc nc nc nc nc nc NJU6624A NJU6624A nju6624b nju6624b -dd ram organization -dd ram organization -panel wiring example -panel wiring example further more, detailed smooth scroll execution are shown at item (i) of instruction further more, detailed smooth scroll execution are shown at item (i) of instruction nju6624b internal ddram nju6624b internal ddram
NJU6624A/b NJU6624A/b (4)instructions (4)instructions the NJU6624A/b incorporates two registers, an instruction register (ir) and a data register(dr). the NJU6624A/b incorporates two registers, an instruction register (ir) and a data register(dr). these two registers store control information temporarily to allow interface between NJU6624A/b and mpu or these two registers store control information temporarily to allow interface between NJU6624A/b and mpu or peripheral ics operating different cycles. peripheral ics operating different cycles. table 4. table of instructions table 4. table of instructions instruction code execute time d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (a) maker testing ms1 ms0 0 1 1 1 1 1 test data - (b) clear display ms1 ms0 0 1 1 0 0 1 * * * * * * * * 234.48us (c) return home ms1 ms0 0 1 0 0 0 1 * * * * * * * * 0us (d) entry mode set ms1 ms0 0 0 1 0 0 0 * * * * * * i/d s 0us (e) display on/off control ms1 ms0 0 0 1 0 0 1 * * * * * d m b 0us (f) address shift ms1 ms0 0 1 0 0 1 0 * * * * * * * arl 0us (g) display shift ms1 ms0 0 0 1 0 1 0 * * * * * * * drl 0us (h) set static port ms1 ms0 0 0 1 0 1 1 * * * * p3 p2 p1 p0 0us (i) contrast control ms1 ms0 0 0 1 1 0 0 * * * * e.v.r. value 0us (j) dot shift ms1 ms0 0 0 1 1 0 1 * * * * * number of dot shift 0us (k) set display mode ms1 ms0 0 0 1 1 1 0 * * * * * * k pd 0us (l) set dd/mk ram address ms1 ms0 0 1 0 0 1 1 * * * dd ram(00 to 0d)h mk ram(10 to 1b)h 0us (m) set cg ram address ms1 ms0 0 1 0 0 0 0 cg ram(00 to fe)h 0us (n) write dd ram data ms1 ms0 0 1 1 0 0 0 write data(dd ram) 41.38us write mk ram data ms1 ms0 0 1 1 0 0 0 * * * write data(mk ram) 41.38us write cg ram data ms1 ms0 0 1 1 0 0 0 * * * write data(cgram) 41.38us (o) read keyscan data ms1 ms0 1 0 0 1 1 1 key data 0us ms1,ms0 : discriminate master or slave. and write code (meet code for selected device) like as mentioned ms1,ms0 : discriminate master or slave. and write code (meet code for selected device) like as mentioned below. below. note : f note : f osc osc =145khz. if the oscillation frequency is changed, the execution time is also changed. =145khz. if the oscillation frequency is changed, the execution time is also changed. ms1 ms0 device 1 0 NJU6624A 0 1 nju6624b
NJU6624A/b NJU6624A/b (4-1)description of each instructions (4-1)description of each instructions (a)maker testing (a)maker testing this code is using for device testing mode ( only for maker ). this code is using for device testing mode ( only for maker ). therefore, please avoid all "0" input or no meaning enable signal input at data "0". therefore, please avoid all "0" input or no meaning enable signal input at data "0". (especially please check the output condition of enable signal when the power turns on.) (especially please check the output condition of enable signal when the power turns on.) (b)clear display (b)clear display when this instruction is executed, the space code (20) when this instruction is executed, the space code (20) h h is written into every dd ram address, the dd ram is written into every dd ram address, the dd ram address (00) address (00) h h is set into the address counter and entry mode is set to increment.the s of entry mode does not is set into the address counter and entry mode is set to increment.the s of entry mode does not change. change. note: the character pattern for character code (20) note: the character pattern for character code (20) h h must be blank code in the user-defined character pattern must be blank code in the user-defined character pattern (custom font). (custom font). (c)return home (c)return home return home instruction is executed, the dd ram address (00) return home instruction is executed, the dd ram address (00) h h is set into the address counter. display is is set into the address counter. display is returned its original position if shifted. the dd ram contents do not change. returned its original position if shifted. the dd ram contents do not change. (d)entry mode set (d)entry mode set entry mode set instruction which sets the address moving direction and display shift on/off, is executed when entry mode set instruction which sets the address moving direction and display shift on/off, is executed when the codes of (i/d) and (s) are written into db the codes of (i/d) and (s) are written into db 1 1 (i/d) and db (i/d) and db 0 0 (s), as shown below. (s), as shown below. (i/d) sets the address increment or decrement, and the (s) sets the whole display shift in the dd ram writing. (i/d) sets the address increment or decrement, and the (s) sets the whole display shift in the dd ram writing. i/d f u n c t i o n 1 address increment: the address of the dd ram or mk ram or cg ram increment ( +1) when the write. 0 address decrement: the address of the dd ram or mk ram or cg ram decrement:( -1) when the write. s f u n c\ t i o n 1 whole display shift. the shift direction is determined by i/d.: shift to the left at i/d=1 and shift to the right at the i/d=0. the display does not shift when writing into cg, mk ram. 0 the display does not shift. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 1 1 1 1 * * * * * * * * d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 1 0 0 1 * * * * * * * * d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 0 0 0 1 * * * * * * * * d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 0 1 0 0 0 * * * * * * i/d s
NJU6624A/b NJU6624A/b (e)display on/off control (e)display on/off control display on/off control instruction which controls the whole display on/off and the addressed position character display on/off control instruction which controls the whole display on/off and the addressed position character blink, is executed when the codes of (d) and (b) are written into db blink, is executed when the codes of (d) and (b) are written into db 2 2 (d) and db (d) and db 0 0 (b), as shown below. (b), as shown below. character font 5 x 7 dots character font 5 x 7 dots alternating display alternating display (1)cursor display example (1)cursor display example (2)blink display example (2)blink display example (f)address shift (f)address shift the the address address shift instruction shifts the shift instruction shifts the address address to the right or left without writing or reading display data. to the right or left without writing or reading display data. d f u n c t i o n 1 display on. 0 display off.i n this mode, the display data remains in the dd ram so that it is retrieved immediately on the display when the d change to 1. b f u n c t i o n 1 the addressed position character is blinking. blinking rate is 500ms at f osc =145khz. the cursor and the blink can be displayed simultaneously. 0 the character does not blink. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 0 1 0 0 1 * * * * * d m b d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 0 0 1 0 * * * * * * * arl when the number of dot-shift is not set ?0? in (j)dot shift instruction, the blink operation will be ap- when the number of dot-shift is not set ?0? in (j)dot shift instruction, the blink operation will be ap- peared at the irregular position. peared at the irregular position. arl f u n c t i o n 0 1 shifts the address position to the left ((ac) is decremented by 1) shifts the address position to the right ((ac) is incremented by 1) m f u n c t i o n 1 icon display on. 0 icon display off.
NJU6624A/b NJU6624A/b (h)set static port (h)set static port it sets static output port signal which can drive led directly it sets static output port signal which can drive led directly like as indicator. like as indicator. initial status is ?l?. initial status is ?l?. (g)display shift (g)display shift the the display display shift instruction shifts the shift instruction shifts the display display to the right or left without writing or reading display data. to the right or left without writing or reading display data. the contents of address counter(ac) does not change by operation of the display shift only. the contents of address counter(ac) does not change by operation of the display shift only. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 0 1 0 1 0 * * * * * * * drl drl f u n c t i o n 0 1 shifts the whole display to the left and the cursor follows it. shifts the whole display to the right and the cursor follows it. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 0 1 0 1 1 * * * * p3 p2 p1 p0 (i)contrast control (i)contrast control contrast control instruction which adjusts the contrast of the lcd,is executed when the code "1" is written into contrast control instruction which adjusts the contrast of the lcd,is executed when the code "1" is written into db db 6 6 and the codes of c and the codes of c 3 3 to c to c 0 0 are written into db are written into db 3 3 to db to db 0 0 as shown below. as shown below. the contrast of lcd can be adjusted one of 16 voltage-stages by setting this 4-bit register. the contrast of lcd can be adjusted one of 16 voltage-stages by setting this 4-bit register. see (5-1) "how to adjust the contrast of lcd". see (5-1) "how to adjust the contrast of lcd". set the binary code "0000" when contrast adjustment is unused. set the binary code "0000" when contrast adjustment is unused. c 3 c 2 c 1 c 0 v lcd 0 0 0 0 low : : 1 1 1 1 high v v lcd lcd = v = v lcd2 lcd2 - v - v ss ss d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 0 1 1 0 0 * * * * c3 c2 c1 c0
NJU6624A/b NJU6624A/b (j)dot shift (j)dot shift the dot shift instruction sets shift line and the number of dot-shift. the dot shift instruction sets shift line and the number of dot-shift. conbination of this instruction and the display shift instruction realize the horizontal smooth scroll. refer to the conbination of this instruction and the display shift instruction realize the horizontal smooth scroll. refer to the following table. following table. sc2 sc1 sc0 f u n c t i o n 0 0 0 no shift. 0 0 1 1dot-shift to the left. 0 1 0 2dot-shift to the left. 0 1 1 3dot-shift to the left. 1 0 0 4dot-shift to the left. 1 0 1 5dot-shift to the left. 1 1 0 don't care. 1 1 1 note1) set 1/d=1, s=0, in the entry mode set, for the line using the smooth scroll function. note1) set 1/d=1, s=0, in the entry mode set, for the line using the smooth scroll function. note2) the number of dot-shift is reset to ?0? by the execution of the display shift instruction. note2) the number of dot-shift is reset to ?0? by the execution of the display shift instruction. note3) only character is shifted by dot shift instruction. note3) only character is shifted by dot shift instruction. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 0 1 1 0 1 * * * * * sc2 sc1 sc0
NJU6624A/b NJU6624A/b -smooth scroll sequence -smooth scroll sequence one out of the following three types of smooth scroll can be selectd by the instructions. one out of the following three types of smooth scroll can be selectd by the instructions. 1dot smooth scroll 1dot smooth scroll 2dot smooth scroll 2dot smooth scroll number of number of dot-shift dot-shift 3dot smooth scroll 3dot smooth scroll d 2 d 1 d 0 3dot-shift 0 1 1 display shift the number of dot- shift is reset to "0" 3dot-shift 0 1 1 number of number of dot-shift dot-shift number of number of dot-shift dot-shift display shift the number of dot- shift is reset to "0" display shift the number of dot- shift is reset to "0" d 2 d 1 d 0 2dot-shift 0 1 0 4dot-shift 1 0 0 4dot-shift 1 0 0 2dot-shift 0 1 0 display shift the number of dot- shift is reset to "0" display shift the number of dot- shift is reset to "0" d 2 d 1 d 0 1dot-shift 0 0 1 2dot-shift 0 1 0 3dot-shift 0 1 1 4dot-shift 1 0 0 5dot-shift 1 0 1 display shift the number of dot- shift is reset to "0" 2dot-shift 0 1 0 3dot-shift 0 1 1 4dot-shift 1 0 0 5dot-shift 1 0 1 1dot-shift 0 0 1
NJU6624A/b NJU6624A/b 00 01 02 ---- 09 0a 0b 0c 0d example of 2 dot smooth scroll example of 2 dot smooth scroll the smooth scroll sequence, which is executed by the 2dot-shift and 4dot-shift instruction, lcd display and dd the smooth scroll sequence, which is executed by the 2dot-shift and 4dot-shift instruction, lcd display and dd ram address movement are shown as follows. ram address movement are shown as follows. power on display on/off write data to dd ram 1ch 2 3 10 11 12 00 01 02 ---- 09 0a 0b 0c 0d setting address in (ac) setting address in (ac) scroll scroll ram ram < lcd display > < lcd display >

ram address set set the address set the address (0c)h to ddram (0c)h to ddram 00 01 02 ---- 09 0a 0b 0c 0d write to ram write character code write character code to the address (0c)h to the address (0c)h (0d)h. (0d)h. note) the address set instruction for scroll ram is not needed later on. note) the address set instruction for scroll ram is not needed later on. for example, the address (0d)? auto-increments to (00)? at the timing of the write to for example, the address (0d)? auto-increments to (00)? at the timing of the write to ram instruction, then the address (00)? returns to 1st line scroll ram position by the ram instruction, then the address (00)? returns to 1st line scroll ram position by the display shift instruction. display shift instruction. dot shift 2dot-shift 2dot-shift 00 01 02 ---- 09 0a 0b 0c 0d 4dot-shift 4dot-shift 01 02 03 ---- 0a 0b 0c 0d 00 display shift seems to execute seems to execute 2dot-shift 2dot-shift 01 02 03 ---- 0a 0b 0c 0d 00 write to ram write character code write character code to the address (00)h. to the address (00)h. 2dot-shift 2dot-shift 01 02 03 ---- 0a 0b 0c 0d 00 4dot-shift 4dot-shift 02 03 04 ---- 0b 0c 0d 00 01 dot shift dot shift dot shift display shift seems to execute seems to execute 2dot-shift 2dot-shift write to ram write character code write character code to the address (00)h. to the address (00)h.
NJU6624A/b NJU6624A/b 00 01 02 03 ---- 09 0a 0b 0c 0d example of 3 dot smooth scroll (NJU6624A+nju6624b 23-character,1-line display) example of 3 dot smooth scroll (NJU6624A+nju6624b 23-character,1-line display) the smooth scroll sequence, which is executed by the 3dot-shift instruction, lcd display and dd ram address the smooth scroll sequence, which is executed by the 3dot-shift instruction, lcd display and dd ram address movement are shown as follows. (NJU6624A(master) and nju6624b(slave) useing.) movement are shown as follows. (NJU6624A(master) and nju6624b(slave) useing.) power on 00 01 02 ---- 09 0a 0b 0c 0d

write the data same as data in the slave address write the data same as data in the slave address (01)h and (02)h into the dd ram address (0c)h, (01)h and (02)h into the dd ram address (0c)h, (0d)h for the master scroll ram. (0d)h for the master scroll ram. dot shift (master, slave) 1ch 2 3 1ch 2 3 NJU6624A internal ddram NJU6624A internal ddram nju6624 binternal ddram nju6624 binternal ddram 10 11 12 13 14 15 10 11 12 13 14 15 21 22 23 21 22 23 to the next page to the next page note) dd ram address for the scroll note) dd ram address for the scroll operations incremented (+1) automatically operations incremented (+1) automatically after the data write operation into ram. after the data write operation into ram. therefore, the address set is not required therefore, the address set is not required after the first address set. after the first address set. 00 01 02 ---- 09 0a 0b 0c 0d 00 01 02 03 ---- 09 0a 0b 0c 0d 00 01 02 ---- 09 0a 0b 0c 0d 00 01 02 03 ---- 09 0a 0b 0c 0d 01 02 03 ---- 0a 0b 0c 0d 00 01 02 03 04 ---- 0a 0b 0c 0d 00 display on/off write data to dd ram(master) ram address set (master) write data to dd ram(slave) set the address set the address (0c)h to ddram(master) (0c)h to ddram(master) write to ram (master) ram address set (slave) set the address set the address (0d)h to ddram(slave) (0d)h to ddram(slave) write to ram (slave) write character code write character code to the address (0d)h. to the address (0d)h. display shift (master, slave) 3dot-shift 3dot-shift (master and slave) (master and slave) seems to execute seems to execute 3dot-shift 3dot-shift
NJU6624A/b NJU6624A/b from the last page from the last page 01 02 03 ---- 0a 0b 0c 0d 00 01 02 03 04 ---- 0a 0b 0c 0d 00 02 03 04 ---- 0b 0c 0d 00 01 02 03 04 05 ---- 0b 0c 0d 00 01 02 03 04 ---- 0b 0c 0d 00 01 02 03 04 05 ---- 0b 0c 0d 00 01 03 04 05 ---- 0c 0d 00 01 02 03 04 05 06 ---- 0c 0d 00 01 02 dot shift (master, slave) write to ram (master) write to ram (slave) 3dot-shift 3dot-shift (master and slave) (master and slave) write character code write character code to the address (00)h. to the address (00)h. display shift (master, slave) seems to execute seems to execute 3dot-shift 3dot-shift dot shift (master, slave) write to ram (master) write to ram (slave) 3dot-shift 3dot-shift (master and slave) (master and slave) write character code write character code to the address (00)h. to the address (00)h. display shift (master, slave) seems to execute seems to execute 3dot-shift 3dot-shift write the data same as the character code in write the data same as the character code in slave address (03)h into the dd ram address slave address (03)h into the dd ram address (00)h for the master scroll ram. (00)h for the master scroll ram. write the data same as the character code in write the data same as the character code in slave address (04)h into the dd ram address slave address (04)h into the dd ram address (01)h for the master scroll ram. (01)h for the master scroll ram.
NJU6624A/b NJU6624A/b (k)set display mode (k)set display mode the set display mode instruction control the function of key scan and power down mode. the set display mode instruction control the function of key scan and power down mode. pd f u n c t i o n 1 power down mode. all of common and segment terminal set the voltage level of vlcd2 0 release the power down mode. k f u n c t i o n 1 key scan on 0 key scan off in busy of keyscan (tks), all of segment terminal (s0 to s7) output the voltage of v2.or v lcd2 in busy of power down mode, do not input any instructions except for release the power down mode. in busy of power down mode, do not input any instructions except for release the power down mode. the power down mode should be set before power off because any irregular display appearance at power off is the power down mode should be set before power off because any irregular display appearance at power off is prevented. prevented. (j)set dd/mk ram address (j)set dd/mk ram address ram address ram address dd ram dd ram : : (00) (00) h h - (0d) - (0d) h h mk ram mk ram : : (10) (10) h h - (1d) - (1d) h h (j)set cg ram address (j)set cg ram address the cg ram address set instruction is executed when the "h" level input to the ac terminal and the address is the cg ram address set instruction is executed when the "h" level input to the ac terminal and the address is written into db written into db 7 7 to db to db 0 0 as shown above. as shown above. the address data (db the address data (db 7 7 to db to db 0 0 ) is written into the address counter (ac) by this instruction. ) is written into the address counter (ac) by this instruction. after this instruction execution, the data writing is performed into the addressed ram. after this instruction execution, the data writing is performed into the addressed ram. the ram includes cg ram address as shown below. the ram includes cg ram address as shown below. ram address ram address cg ram cg ram : : (00) (00) h h - (fe) - (fe) h h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 0 0 1 1 * * * ad4 ad3 ad2 ad1 ad0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 0 1 1 1 0 * * * * * * k pd the address data (db the address data (db 4 4 to db to db 0 0 ) is written into the address counter (ac) by this instruction. ) is written into the address counter (ac) by this instruction. after this instruction execution, the data writing is performed into the addressed after this instruction execution, the data writing is performed into the addressed dd/mk dd/mk ram. ram. the ram includes dd ram and mk ram, and these rams are shared by address as shown below. the ram includes dd ram and mk ram, and these rams are shared by address as shown below. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 0 0 0 0 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 the key scan operation when switching to the power down mode during key scan. the key scan operation when switching to the power down mode during key scan. when switching to the power down mode during key scan operation, it stops key scan operation when switching to the power down mode during key scan operation, it stops key scan operation in the period and after power down mode cancellation too. in the period and after power down mode cancellation too. after power down mode cancellation, the req signal maintains "h" when detects key-in signal after power down mode cancellation, the req signal maintains "h" when detects key-in signal before switches to power down mode and req signal rises to"h". before switches to power down mode and req signal rises to"h". however, the key scan operation becomes invalid data even if it reads key-in data because however, the key scan operation becomes invalid data even if it reads key-in data because it stoppd.the key data becomes to valid with the key scan by the next key scan of frame. it stoppd.the key data becomes to valid with the key scan by the next key scan of frame.
NJU6624A/b NJU6624A/b (n)write data to cg, dd or mk ram (n)write data to cg, dd or mk ram -write data to dd ram -write data to dd ram -write data to mk ram -write data to mk ram by the execution of this instruction, the binary 8-bit data (a by the execution of this instruction, the binary 8-bit data (a 7 7 to a to a 0 0 ) are written into the dd ram, and the binary 5- ) are written into the dd ram, and the binary 5- bit data (a bit data (a 4 4 to a to a 0 0 ) are written into the cg or mk ram. the selection of ram is determined by the previous in- ) are written into the cg or mk ram. the selection of ram is determined by the previous in- struction. after this instruction execution, the address increment (+1) or decrement(-1) is performed automatically struction. after this instruction execution, the address increment (+1) or decrement(-1) is performed automatically according to the entry mode set. and the display shift is also executed according to the previous entry mode set. according to the entry mode set. and the display shift is also executed according to the previous entry mode set. however, the data in mk ram (1c)h and (1d)h are not displayed, bat the automatic address increment is per- however, the data in mk ram (1c)h and (1d)h are not displayed, bat the automatic address increment is per- formed. and the display is not changed by the data written into mk ram (1c)h and (1d)h formed. and the display is not changed by the data written into mk ram (1c)h and (1d)h (o)read data key (o)read data key read data key is a instruction for data reading out of keyscan. however, the bit 8 to 15 are input data. after this 8- read data key is a instruction for data reading out of keyscan. however, the bit 8 to 15 are input data. after this 8- bit data were input, the operation change to output from input at the falling edge of 8th sck clock. bit data were input, the operation change to output from input at the falling edge of 8th sck clock. -write data to cg ram -write data to cg ram d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 1 0 0 0 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 0 0 0 0 * * * dm4 dm3 dm2 dm1 dm0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 0 1 0 0 0 0 * * * dc4 dc3 dc2 dc1 dc0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 code ms1 ms0 1 0 0 1 1 1 kl3 kl2 kl1 kl0 0 kh2 kh1 kh0
NJU6624A/b NJU6624A/b (4-2)initialization by instruction (4-2)initialization by instruction if the power supply conditions for the correct operation of the internal reset circuits are not satisfied, the if the power supply conditions for the correct operation of the internal reset circuits are not satisfied, the NJU6624A/b must be initialized by the instruction. NJU6624A/b must be initialized by the instruction. initialized. initialized. no display appears. no display appears. note : when the icon display function using, the system should be initialized by software initialization. note : when the icon display function using, the system should be initialized by software initialization. d15 d14 d13 d12 d11 d10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display off ms1 ms0 0 0 1 0 0 1 * * * * * 0 0 0 entry mode set ms1 ms0 0 0 1 0 0 0 * * * * * * i/d s set static port ms1 ms0 0 0 1 0 1 1 * * * * p3 p2 p1 p0 contrast control ms1 ms0 0 0 1 1 0 0 * * * * c3 c2 c1 c0 set display mode ms1 ms0 0 0 1 1 1 0 0 0 0 0 0 0 k pd clear display ms1 ms0 0 1 1 0 0 1 * * * * * * * * power on wait more than 1.5ms after v dd rises to 2.4v write data to the dd, cg or mk ram and set the instruction
NJU6624A/b NJU6624A/b ( ( 5)lcd display 5)lcd display (5-1)bleeder resistance (5-1)bleeder resistance each lcd driving voltage ( v each lcd driving voltage ( v 1 1 , v , v 2 2 , v , v 3 3 , v , v 4 4 ) is ) is lcd driving high voltage input to the vlcd1 terminal, lcd driving high voltage input to the vlcd1 terminal, generated by generated by the e.v.r. and high impedance bleeder resistance. the e.v.r. and high impedance bleeder resistance. the bleeder resistance is set 1/4 bias suitable for 1/8 duty ratio. the bleeder resistance is set 1/4 bias suitable for 1/8 duty ratio. the capacitor connected between vlcd2 and v the capacitor connected between vlcd2 and v ss ss is needed for stabilizing vlcd. the determination of the each is needed for stabilizing vlcd. the determination of the each capacitance requires to operate with the lcd panel actually. capacitance requires to operate with the lcd panel actually. 1 frame = 6.90(us) x 224 x 8 = 12.36(ms) 1 frame = 6.90(us) x 224 x 8 = 12.36(ms) frame frequency = 1 / 12.36(ms) = 79.50(hz) frame frequency = 1 / 12.36(ms) = 79.50(hz) key scan time = 220.70(us) key scan time = 220.70(us) com1 com1 vlcd vlcd v1 v1 v4 v4 v2 v2 224clocks icon 1 2 3 .............. 7 key icon 1 2 3 .............. 7 key icon 1 2 1 frame 1 frame as the NJU6624A/b incorporate oscillation capacitor and resistor for cr oscillation, 145khz oscillation is avail- as the NJU6624A/b incorporate oscillation capacitor and resistor for cr oscillation, 145khz oscillation is avail- able without any external components. able without any external components. the lcd frame frequency example mentioned below is based on 145khz oscillation.(1clock =6.90us) the lcd frame frequency example mentioned below is based on 145khz oscillation.(1clock =6.90us) (5-2)relation between oscillation frequency and lcd frame frequency (5-2)relation between oscillation frequency and lcd frame frequency vss vss lcd driving voltage vs duty ratio lcd driving voltage vs duty ratio power supply duty ratio 1/8 bias 1/4 v lcd vlcd2- vss v v lcd lcd is the maximum amplitude for lcd driving voltage. is the maximum amplitude for lcd driving voltage. + + + + internal nju6624 internal nju6624 vss vss e.v.r.(16step) e.v.r.(16step) v1 v1 v2 v2 (v3) (v3) v4 v4 vlcd2 vlcd2 vlcd1 vlcd1 5k 5k vlcd vlcd vlcd vlcd 4k 4k 4k 4k 4k 4k 4k 4k vss vss v1 v1 v2 v2 v4 v4
NJU6624A/b NJU6624A/b (6)interface with mpu (6)interface with mpu the instructions and data are communicated with the serial port which is a clock synchronization type based on the instructions and data are communicated with the serial port which is a clock synchronization type based on 16-bit per word. 16-bit per word. the NJU6624A/b can be controlled by the serial data as shown below. the NJU6624A/b can be controlled by the serial data as shown below. the serial interface circuit operates in cs=l. the serial interface circuit operates in cs=l. a communication unit consists of 16-bit data. the communication period is from the falling edge of cs terminal to a communication unit consists of 16-bit data. the communication period is from the falling edge of cs terminal to the rising edge. the inputs data and latched at rising edge of shift clock (scl) and the first 16-bit data are fetched the rising edge. the inputs data and latched at rising edge of shift clock (scl) and the first 16-bit data are fetched into the NJU6624A/b at the rising edge of chip select (cs). the data over than 16 bits are ignored. if the input into the NJU6624A/b at the rising edge of chip select (cs). the data over than 16 bits are ignored. if the input data are less than 16 bits,they are ignored at the rising edge of "cs". therefore,just 16 bits data should be input data are less than 16 bits,they are ignored at the rising edge of "cs". therefore,just 16 bits data should be input for the correct communication. in case of ram data input, the ram address is changed automatically for the correct communication. in case of ram data input, the ram address is changed automatically as increment or decrement. as increment or decrement. the data to input is msb first. although the output data is just only key scan, data bits d8 to d15 in the key data the data to input is msb first. although the output data is just only key scan, data bits d8 to d15 in the key data read out instruction are input. after these 8-bit instruction is input, this serial data input terminal is changed to the read out instruction are input. after these 8-bit instruction is input, this serial data input terminal is changed to the output terminal at the 8th falling edge of scl clock. output terminal at the 8th falling edge of scl clock. the electrical short between the NJU6624A/b and external circuit must be prevented in the application. the electrical short between the NJU6624A/b and external circuit must be prevented in the application. cs cs scl scl data data
NJU6624A/b NJU6624A/b g g absolute maximum ratings absolute maximum ratings g g electrical characteristics electrical characteristics (vdd=4.5v to 5.5v,ta=-40 to +80 (vdd=4.5v to 5.5v,ta=-40 to +80 o o c c ) ) p a r a m e t e r symbol c o n d i t i o n s min. typ. max. unit note input voltage vih1 0.8vdd - vdd v 4 vil1 vss - 0.2vdd v 4 input voltage vih2 0.8vdd - vlcd1 v 5 vil2 vss - 0.2vdd v 5 output voltage voh -ioh=2ma,vdd=5v 4.0 - - v 6 vol iol=2ma,vdd=5v - - 0.5 v 6 driver on-resist.(com) rcom + id=1ua(com terminal) vo=vlcd,vss,v1,v4 - - 40 k w 8 driver on-resist.(seg) rseg + id=1ua(seg terminal) vo=vlcd,vss,v2 - - 40 k w 8 pull-up mos current 1 -ip1 vdd=8v 5 25 50 ua 5 pull-up mos current 2 -ip2 vlcd1=8v 10 25 50 ua 5 input leakage current ili vin=0 to vdd -1.0 - 1.0 ua 10 operating current idd1 vdd=5v fosc=145khz ta=25 o c, display, keyscanon - - 500 ua 7 idd2 vdd=5v, ta=25 o c stand-by mode - 7 10 ua 7 bleeder resistan- ce circuit lcd driving voltage v1 vlcd1-vss=8v,ta=25 o c e.v.r. value "1111" com/seg terminal 5.8 6.0 6.2 v v2 3.8 4.0 4.2 v v4 1.8 2.0 2.2 v bleeder resistance rb vlcd1-vss=8v,ta=25 o c e.v.r. value "1111" 11.2 16.0 20.8 k w oscillation frequency fosc vdd=5v,ta=25 o c 72 145 218 khz lcd display voltage vlcd1 vlcd1 terminal,vss=0v vdd - 10.0 v 9 vcd1 current ilcd1 vlcd1-vss=8v 1 ma (ta=25 (ta=25 o o c) c) p a r a m e t e r symbol r a t i n g s unit note supply voltage(1) vdd -0.3 to +7.0 v supply voltage(2) vlcd1 vss+10.5 to vss+0.3 v vlcd1 terminal input voltage v in -0.3 to vdd+0.3 v operating temperature topr -40 to +85 o c storage temperature tstg -55 to +125 o c power dissipation pd 500 mw note 1 : if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. note 1 : if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. using the lsi within electrical characteristics is strongly recommended for normal operation. use beyond using the lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause mal function and poor reliability. the electric characteristics conditions will cause mal function and poor reliability. note 2 : decoupling capacitor should be connected between v note 2 : decoupling capacitor should be connected between v dd dd and v and v ss ss , v , v lcd1 lcd1 -v -v ss ss due to the stabilized due to the stabilized operation for the voltage converter. operation for the voltage converter. note 3 : all voltage values are specified as v note 3 : all voltage values are specified as v ss ss = 0v = 0v the relation : v the relation : v lcd1 lcd1 3 3 v v lcd2 lcd2 > v > v dd dd > v > v ss ss , v , v ss ss =0v must be maintained. =0v must be maintained.
NJU6624A/b NJU6624A/b note 6 : apply to the p0 to p3, req, data terminals. note 6 : apply to the p0 to p3, req, data terminals. note 7 : if the input level is medium, current consumption will increase due to the penetration current. therefore, note 7 : if the input level is medium, current consumption will increase due to the penetration current. therefore, the input level must be fixed to "h" or "l". the input level must be fixed to "h" or "l". note 4 : note 4 : apply to the osc1, scl, data, cs, reset terminals. apply to the osc1, scl, data, cs, reset terminals. note 5 : note 5 : ?pull-up mos current 1? : apply to the data terminals. ?pull-up mos current 1? : apply to the data terminals. ?pull-up mos current 2? and ?input voltage 2? : apply to the k0 to k3 terminals. ?pull-up mos current 2? and ?input voltage 2? : apply to the k0 to k3 terminals. a -operating current measurement circuit -operating current measurement circuit vdd vdd vss vss nju6624 nju6624 5v 5v note 8 : r note 8 : r com com and r and r com com are the resistance values between power supply terminals (v are the resistance values between power supply terminals (v ss, ss, vlcd2 or v vlcd2 or v 1 1 ,v ,v 2 2 ,v ,v 4 4 ) and ) and each common terminal (com each common terminal (com 1 1 to com to com 7 7 /commk) and supply voltage (v /commk) and supply voltage (v ss ss , vlcd2 or v , vlcd2 or v 1 1 ,v ,v 2 2 ,v ,v 4 4 ) and each ) and each segment terminal (seg segment terminal (seg 1 1 to seg to seg 71 71 ) respectively, and measured when the current i ) respectively, and measured when the current i d d is flown on every is flown on every common and segment terminals at a same time. common and segment terminals at a same time. note 9 : apply to the output voltage from each com and seg are less than note 9 : apply to the output voltage from each com and seg are less than + + 0.15v against the lcd driving 0.15v against the lcd driving constant voltage (v constant voltage (v dd dd , v , v lcd1 lcd1 ) at no load condition. ) at no load condition. note 10: apply to the note 10: apply to the scl,cs,reset terminals. scl,cs,reset terminals.
NJU6624A/b NJU6624A/b -serial interface sequence -serial interface sequence (v (v dd dd =4.5v to 5.5v, vlcd1=v =4.5v to 5.5v, vlcd1=v ss ss +8.0v, ta=25 +8.0v, ta=25 o o c) c) g g bus timing characteristics bus timing characteristics p a r a m e t e r symbol min. max. condition unit serial clock cycle time t cyce 1 - fig.1 us serial clock width t sc 300 - ns chip select pulse width pw cs 100 - us chip select set up time t csu 300 - ns chip select hold time 1 t ch1 300 - ns serial input data set up time t sisu 300 - ns serial input data hold time t sih 300 - ns key data output delay time t kdd - 300 fig.2 ns data port direction change time from input to output t srwd - 300 ns data port direction change time from output to input t crwd - 300 ns chip select hold time 2 t ch2 1 - us input data sequence input data sequence c s d a t a s c l t c y c e t s i s u t s c p w c s t c h t s c t s i h t c s u input data sequence input data sequence c s d a t a s c l t c h 2 t k d d t s r w d 8 9 1 0 t c r w d 1 5 1 6 i n p u t d a t a i / o c h a n g e t i m i n g o u t p u t o u t p u t o u t p u t o u t p u t i n p u t
NJU6624A/b NJU6624A/b - - the input condition when using the hardware reset circuit the input condition when using the hardware reset circuit reset reset vil vil trsl trsl - - power supply condition when using the internal initialization circuit power supply condition when using the internal initialization circuit (ta=25 (ta=25 o o c) c) since the internal initialization circuits will not operate normally unless the above conditions are met, in such a since the internal initialization circuits will not operate normally unless the above conditions are met, in such a case initialize by instruction. (refer to initialization by the instruction) case initialize by instruction. (refer to initialization by the instruction) vdd vdd 0.2v 0.2v toff toff trdd trdd 0.1ms < trdd < 5ms 0.1ms < trdd < 5ms toff > 1ms toff > 1ms 2.4v 2.4v 0.2v 0.2v 0.2v 0.2v p a r a m e t e r symbol condition min typ max unit reset input "0" level width t rsl fosc=1 45 khz 1.2 - - ms -keyscan timing -keyscan timing s0 s0 tkp tkp tks tks s1 s1 s7 s7 vlcd2/2 vlcd2/2 vlcd2/2 vlcd2/2 vlcd2/2 vlcd2/2 (f (f osc osc =145khz) =145khz) p a r a m e t e r symbol condition min typ max unit power supply rise time t rdd - 0.1 - 5 ms power supply off time t off - 1 - - ms p a r a m e t e r symbol condition min typ max unit keyscan time t rdd - - 221 - us keyscan palse width t off - - 27.6 - us = = = = = =
NJU6624A/b NJU6624A/b g g lcd driving wave form lcd driving wave form com1 com1 com2 com2 com3 com3 com4 com4 com5 com5 com6 com6 com7 com7 commk commk seg seg 1 2 3 4 5 1 2 3 4 5 is keyscan wave form is keyscan wave form commk commk mark 1 2 3 ........... 7 key scan mark 1 2 3 ......... 7 key scan mark 1 2 . . . . . . . com1 com1 com2 com2 com8 com8 seg1 seg1 seg2 seg2 vlcd vlcd v1 v1 vss vss v4 v4 v2 v2 vlcd vlcd v1 v1 vss vss v4 v4 v2 v2 vlcd vlcd v1 v1 vss vss v4 v4 v2 v2 vlcd vlcd v1 v1 vss vss v4 v4 v2 v2 vlcd vlcd v1 v1 vss vss v4 v4 v2 v2 vlcd vlcd v1 v1 vss vss v4 v4 v2 v2
NJU6624A/b NJU6624A/b NJU6624A/b NJU6624A/b req req data data scl scl cs cs reset reset vdd vdd vlcd1 vlcd1 vlcd2 vlcd2 v1 v1 v2 v2 v4 v4 vss vss commk commk com1 com1 com7 com7 seg1 seg1 seg71 seg71 mcu mcu p3 p0 p3 p0 k3 k2 k1 k0 s7 s6 s5 s4 s3 s2 s1 k3 k2 k1 k0 s7 s6 s5 s4 s3 s2 s1 vdd vdd vlcd1 vlcd1 lcd panel lcd panel (12-character (12-character 1-line+icon) 1-line+icon) application circuits application circuits (1) 12-character 1-line display example (1) 12-character 1-line display example + + + + + + + + + +
NJU6624A/b NJU6624A/b NJU6624A NJU6624A req req data data scl scl cs cs reset reset vdd vdd vlcd1 vlcd1 vlcd2 vlcd2 v1 v1 v2 v2 v4 v4 vss vss + + + + + + + + req req data data scl scl cs cs reset reset vdd vdd vlcd1 vlcd1 vlcd2 vlcd2 v1 v1 v2 v2 v4 v4 vss vss nju6624b nju6624b commk commk com1 com1 com7 com7 seg1 seg1 seg71 seg71 commk commk com1 com1 com7 com7 seg1 seg1 seg71 seg71 mcu mcu p3 p0 p3 p0 k3 k2 k1 k0 s7 s6 s5 s4 s3 s2 s1 k3 k2 k1 k0 s7 s6 s5 s4 s3 s2 s1 p3 p0 p3 p0 k3 k2 k1 k0 s7 s6 s5 s4 s3 s2 s1 k3 k2 k1 k0 s7 s6 s5 s4 s3 s2 s1 vdd vdd vlcd1 vlcd1 + + lcd panel lcd panel (12-character (12-character 1-line+icon) 1-line+icon) lcd panel lcd panel (12-character (12-character 1-line+icon) 1-line+icon) (2) 12-character 2-line display example (2) 12-character 2-line display example
m e m o [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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